|
Orio Bellezza was born in Bergamo (Italy) in 1959. He graduated with honors in Chemistry from Milan University in 1983, having written his thesis in Theoretical Chemical-Physics.
Bellezza joined SGS-ATES, a precursor company to STMicroelectronics, in 1984 as a Process Engineer, and spent the first two years contributing to the opening of Module 6, the Company�s first 6-inch wafer fab, at the Company�s headquarters in Agrate Brianza (Italy). Then, he moved to the Central R&D department, where he worked as a Development Engineer in various technical areas. Bellezza subsequently became the Process Integration Manager, responsible for submicron EPROM (Erasable Programmable Read-Only Memories) process technology modules. In this role, he published technical papers and earned several patents in non-volatile memories.
In 1996, Bellezza was promoted to the role of Director of the Agrate R1 Research and Development facility, responsible for both manufacturing and development activities. Here, he led the wafer fab�s conversion to 200mm diameter wafers and led the ramp-up of the R2 Technology Center. In 2002, Bellezza was promoted to Vice President of Central R&D. Under his leadership, ST�s Agrate R2 developed, manufactured and ultimately transferred to other ST wafer fabs several generations of non-volatile memory and smart-power technologies.
In 2005, Bellezza was promoted to Vice President and Assistant General Manager of Front-End Technology and Manufacturing (the most sophisticated part of the wafer manufacturing process), managing the Agrate R2 and other R&D teams around the world. He also served on the Board of the ST-Hynix memory-manufacturing joint venture, established in Wuxi (China).
In January 2008, Bellezza was promoted to the post of General Manager, Front-End Manufacturing, where he is responsible for all of ST�s wafer fabrication operations and facilities.
Bellezza is a member of the ST�s Executive Committee, comprised of ten senior corporate executives in addition to the COO and the CEO. | 